/*
 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <arch_helpers.h>
#include <bl_common.h>
#include <console.h>
#include <tegra_def.h>
#include <tegra_private.h>
#include <xlat_tables.h>

/*******************************************************************************
 * The Tegra power domain tree has a single system level power domain i.e. a
 * single root node. The first entry in the power domain descriptor specifies
 * the number of power domains at the highest power level.
 *******************************************************************************
 */
const unsigned char tegra_power_domain_tree_desc[] = {
    /* No of root nodes */
    1,
    /* No of clusters */
    PLATFORM_CLUSTER_COUNT,
    /* No of CPU cores - cluster0 */
    PLATFORM_MAX_CPUS_PER_CLUSTER,
    /* No of CPU cores - cluster1 */
    PLATFORM_MAX_CPUS_PER_CLUSTER
};

/* sets of MMIO ranges setup */
#define MMIO_RANGE_0_ADDR    0x50000000
#define MMIO_RANGE_1_ADDR    0x60000000
#define MMIO_RANGE_2_ADDR    0x70000000
#define MMIO_RANGE_SIZE        0x200000

/*
 * Table of regions to map using the MMU.
 */
static const mmap_region_t tegra_mmap[] = {
    MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
            MT_DEVICE | MT_RW | MT_SECURE),
    MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
            MT_DEVICE | MT_RW | MT_SECURE),
    MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
            MT_DEVICE | MT_RW | MT_SECURE),
    {0}
};

/*******************************************************************************
 * Set up the pagetables as per the platform memory map & initialize the MMU
 ******************************************************************************/
const mmap_region_t *plat_get_mmio_map(void)
{
    /* MMIO space */
    return tegra_mmap;
}

/*******************************************************************************
 * Handler to get the System Counter Frequency
 ******************************************************************************/
unsigned int plat_get_syscnt_freq2(void)
{
    return 19200000;
}

/*******************************************************************************
 * Maximum supported UART controllers
 ******************************************************************************/
#define TEGRA210_MAX_UART_PORTS        5

/*******************************************************************************
 * This variable holds the UART port base addresses
 ******************************************************************************/
static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = {
    0,    /* undefined - treated as an error case */
    TEGRA_UARTA_BASE,
    TEGRA_UARTB_BASE,
    TEGRA_UARTC_BASE,
    TEGRA_UARTD_BASE,
    TEGRA_UARTE_BASE,
};

/*******************************************************************************
 * Retrieve the UART controller base to be used as the console
 ******************************************************************************/
uint32_t plat_get_console_from_id(int id)
{
    if (id > TEGRA210_MAX_UART_PORTS)
        return 0;

    return tegra210_uart_addresses[id];
}

/*******************************************************************************
 * Initialize the GIC and SGIs
 ******************************************************************************/
void plat_gic_setup(void)
{
    tegra_gic_setup(NULL, 0);
}
